Compensating method for a PLL circuit that functions according to the two-point principle, and PLL circuit provided with a compensating device

ABSTRACT

A PLL circuit is tuned to a first frequency by using a first digital modulation signal and subsequently tuned to a second frequency by using a second digital modulation signal. A differential signal, that is a function of the change in voltage of a VCO control signal generated by the modulation signals, is compared with a comparison signal, that is characteristic of the analog modulation amplitude. Based on the comparison the analog modulation amplitude is changed to minimize or substantially eliminate a deviation between the signals.

RELATED APPLICATION

This application is a National Stage filing of International ApplicationNo. PCT/DE02/02709, filed Jul. 24, 2002, which is entitled “Compensatingmethod for a PLL circuit that functions according to the two-pointprinciple, and PLL circuit provided with a compensating device”, whichwas not published in English, that claims priority to German PatentApplication No. 101 47 963.8 filed on Sep. 28, 2001, and both are herebyincorporated by reference in their entirety.

FIELD OF THE INVENTION

The invention relates to a compensating method for a PLL circuit thatfunctions according to the two-point principle and to a PLL circuitdesigned according to the principle of two-point modulation and providedwith a compensating device.

BACKGROUND OF THE INVENTION

A transmitter concept that can be implemented with little complexity fortransceivers in mobile radio systems is offered by transmitters whichhave a modulator that functions according to the known principle oftwo-point modulation. A PLL (Phase Locked Loop=follow-upsynchronization) circuit is used in this case as a frequencysynthesizer, and is used for the phase or frequency modulation of ahigh-frequency signal.

The modulation signal is usually injected into the PLL circuit via aprogrammable frequency divider contained in the feedback path of the PLLloop. A digital modulation signal is used in this case, and is used forcontinually reprogramming the digital frequency divider. This form ofmodulation, which is also referred to as single-point modulation, isknown for example from the Patent Specifications U.S. Pat. No.4,965,531, U.S. Pat. No. 6,008,703 and U.S. Pat. No. 6,044,124.

To achieve low noise of the PLL circuit, the bandwidth of the circuit ismade much smaller than is required for the transmission of the modulateddata. Therefore, in addition to the purely digital modulation, an analogmodulation is also used to compensate for the restricted bandwidth. Thesimultaneous injection of a digital modulation signal and an analogmodulation signal into a PLL circuit is referred to as two-pointmodulation.

The injection of the digital and analog modulation signals takes placeat two different points of the PLL circuit. What is important for theway in which the two-point modulation operates is that, apart from beingsynchronized in phase, a high degree of coincidence of the amplitudes ofthe two modulation signals used is required. However, on account ofproduction tolerances of the components for the analog modulation,fluctuations occur in the modulation gradient and the amplitude level ofthe modulation. For this reason, it is necessary to perform an amplitudecompensation between the analog modulation signal and the digitalmodulation signal once the PLL circuit has been produced.

If temperature influences additionally have to be taken into account,such a compensation has to be carried out before each transmittingoperation.

A two-point modulator and a method for phase and frequency modulationwith a PLL circuit is described in the German Laid-open PatentApplication DE 199 29 167 A1. The modulation in this case takes place inthe first instance at a point of the PLL circuit at which high-passtransmission characteristics are obtained for the modulation frequency.In addition, the modulation takes place at a second point of the PLLcircuit, at which low-pass transmission characteristics are obtained forthe modulation frequency. The modulation with low-pass transmissioncharacteristics takes place digitally in a frequency divider in thefeedback path of the PLL circuit.

A know method for compensating a PLL circuit with two-point modulationcomprises impressing the two-point modulation of the circuit in thesteady state and using an external measuring receiver to receive anddemodulate the signal that is sent. Depending on the demodulation resultobtained, a compensation of the digital and analog modulation signals isperformed. However, on account of the non-linear behavior of theoscillation-generating element—of a voltage-controlled oscillator VCO—ofthe PLL circuit with regard to the frequency as a function of thecontrol voltage, this compensation must be performed for each channel.For a relatively large number of channels, this results in acorrespondingly long measuring time. In addition, the compensationinformation must be stored in a memory. It can be regarded as a furtherdisadvantage that the influence of temperature changes is not taken intoaccount in this method.

The receiving and demodulating of the signal generated by the PLLcircuit can also be performed by the receiving part of the transceiver.However, this increases the complexity of the circuitry in adisadvantageous way, since this would require a complete second PLLcircuit in the receiver.

In the document WO 99/07065 there is a description of a compensatingmethod for a PLL that functions according to the principle of two-pointmodulation. In this method, the PLL is tuned to different frequencies byspecifying different divider values N, and the corresponding voltagevalues at the input of the VCO are recorded. The pairs of valuesdetermined in this way are used to calculate the characteristic of theVCO. The characteristic is evaluated by means of a processor, andscaling values for setting the modulation amplitude of the analogmodulation signal are thereby determined.

SUMMARY OF THE INVENTION

The object of the invention is to provide a compensating method for aPLL circuit with which rapid and exact amplitude compensation can beachieved between the digital modulation signal and the analog modulationsignal. Furthermore, the invention aims at providing a PLL circuit witha compensating device, in which a rapid and exact amplitude compensationof the modulation signals can be achieved with a relatively simplecircuit arrangement.

In the case of a compensating method for a PLL circuit that functionsaccording to the principle of two-point modulation, the PLL circuit istuned to a first frequency by injecting a first digital modulationsignal. Subsequently, a second digital modulation signal is injectedinto the PLL circuit, the PLL circuit being tuned to a second frequency,which deviates from the first frequency. A differential signal, which ischaracteristic of the change of a control signal of afrequency-generating unit of the PLL circuit that is brought about bythe two digital modulation signals, is generated and coupled out fromthe PLL circuit. The differential signal is compared with a comparisonsignal, which is characteristic of a modulation amplitude of an analogmodulation signal, and, dependent on the deviation that is determined inthe comparison, the modulation amplitude is changed to eliminate thedeviation.

This allows the effect be achieved in the compensating method accordingto the invention that the demodulating of the output signal generated bythe PLL circuit for compensating purposes is no longer required, sincecompensating relies on a deviation between two digital modulationsignals that is represented by a differential signal which ischaracteristic of the deviation. Furthermore, this allows the effect tobe achieved that a relatively exact and rapid compensation can becarried out.

An advantageous exemplary embodiment of the compensating methodaccording to the invention is characterized in that the first digitalmodulation signal is injected in such a way that the PLL circuit istuned to a first frequency, which is formed by subtracting a frequencyof a variably selectable, digital modulation amplitude from a channelcenter frequency. If the injection of the second digital modulationsignal then causes the PLL circuit to be tuned to a second frequency,which is formed by adding the frequency of the variably selectable,digital modulation amplitude and the channel center frequency, apreferred variant of the configuration is characterized in that avoltage value corresponding to the analog modulation signal ismultiplied by a factor of 2 for the comparison with the voltage valuecorresponding to the differential signal. This allows the effect beachieved that an analog voltage value corresponding to the differentialsignal can be relatively high and, as a result, deviations between thedigital modulation and the analog modulation can be compensatedrelatively exactly.

According to a preferred design, a compensating path contributing to thecontrol signal generation is connected in parallel with a main path ofthe PLL circuit. In this case, an advantageous variant of the method ischaracterized in that the compensating path is activated at least duringthe injection of the second digital modulation signal.

Furthermore, it may be provided in an advantageous way that the mainpath of the PLL circuit is deactivated after the injection of the firstdigital modulation signal, in that a current generated by a first chargepump in the main path is set to the value of zero. This achieves theeffect that a voltage corresponding to the first digital modulationsignal at a tuning input of a VCO remains substantially constant duringthe steps which follow (second injection step and, if appropriate,compensating step).

However, maintaining the voltage generated during the first injectionstep at the tuning input of the VCO can generally also be accomplishedin a different way. A advantageous exemplary embodiment is zed in thatthe main path of the PLL circuit is kept active after the injection ofthe first digital modulation signal and a current is set by the chargepump in the main path of the PLL circuit in such a way that the voltageat the tuning input of the VCO is kept substantially constant. This canachieve the effect that changing of the voltage (generated during thefirst injection step) at the tuning input of the VCO on account ofleakage currents in the main path is prevented during the compensation.

A further aspect of the invention relates to a PLL circuit which isformed for the injection of an analog modulation signal and a digitalmodulation signal according to the principle of two-point modulation.Connected in parallel with a main path of the PLL circuit is acompensating path, which comprises a coupling-out means for generating adifferential signal, which is characteristic of the change of a controlsignal of a frequency-generating unit when different digital modulationsignals are injected into the PLL circuit. Furthermore, the compensatingpath comprises a comparison unit for comparing the differential signalwith a comparison signal, which is characteristic of a modulationamplitude of an analog modulation signal, and a modulation unit, whichchanges the modulation amplitude in dependence on an output signal ofthe comparison unit.

The PLL circuit according to the invention, with the main path and thecompensating path connected in parallel, provides a relatively simpleand low-complexity circuit arrangement, with which a rapid and exactcompensation of the digital modulation signal and the analog modulationsignal can be carried out.

In the case of an advantageous exemplary embodiment, it may be providedthat the differential signal can be applied by means of a first switchto a modulation input of a VCO of the PLL circuit. Furthermore, it maybe provided that the compensating path has a second switch, in theclosed position of which the compensation signal is present at an inputof the comparison unit.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in more detail below on the basis of anexemplary embodiment with reference to the drawing, in which:

FIG. 1 shows a block diagram of a PLL circuit according to the inventionwith a compensating device, and

FIG. 2 shows a schematic flow diagram of the compensating methodaccording to the invention.

DETAILED DESCRIPTION OF THE INVENTION

A PLL circuit 1 (FIG. 1) that functions according to the principle oftwo-point modulation is electrically connected to a modulation device 2and a compensating path 3. The PLL circuit 1 has in its main path aphase detector (PFD=Phase Frequency Detector) 11, a first charge pump(CP1=Charge Pump 1) 12, a first loop filter (LP1=Loop Filter 1) 13 and avoltage-controlled oscillator (VCO=Voltage Controlled Oscillator) 14.The loop filter 13 is configured as a low-pass filter, wherebyhigher-frequency signal components are smoothed. The VCO 14 representsthe oscillation-generating component in the PLL circuit 1 and has asummation point 141 and a frequency-generating unit 142. The PLL circuit1 is closed by means of a feedback path, which extends from the outputof the VCO 14 to an input of the PFD 11 and in which a programmablefrequency divider (DIV=Divider) 15 is arranged. The DIV 15 may beconfigured for example as a fractional−N frequency divider, whereby afrequency division by a non-integral number is also made possible.

For the preprocessing of a modulation signal MS, the modulation device 2has a programming unit 21 and a digital/analog converter (DAC=DigitalAnalog Converter) 22.

Connected in parallel with the main path of the PLL circuit 1 is thecompensating path 3. The compensating path 3 has a second charge pump(CP2) 33 and a second loop filter (LP2) connected downstream of thecharge pump 33. Furthermore, a comparison unit 31 and an analogmodulation unit 32 are arranged in the compensating path 3. Depending onthe compensating operation carried out, the comparison unit 31 and theanalog modulation unit 32 are electrically connected by means of a firstswitch 35 to a modulation input ME of the VCO 14 of the PLL circuit 1.By means of a second switch 36, the output of the analog modulation unit32 can be fed back to a second input of the comparison unit 31. Thissignal path between the modulation unit 32 and the comparison unit 31also has a multiplier 37.

In the two-point modulation, an analog modulation signal and a digitalmodulation signal are impressed on the PLL circuit 1 via the modulationdevice 2. Since the analog modulation signal is affected by drift andtolerances, by contrast with the digital modulation signal which doesnot have any tolerances on account of its discrete nature, it isnecessary to compensate the two modulation signals with regard to theiramplitudes.

A modulation signal MS, which in the exemplary embodiment is given theform of a digital signal, is added at a summation point 4 to a carriersignal TS on which the PLL frequency synthesis is based. The resultingsignal 5 is present at an input of the programming unit 21.

The programming unit 21, which in the exemplary embodiment is configuredas a sigma-delta modulator, generates at its output a first digitalmodulation signal 6, which is present at a second input of the DIV 15.The digital modulation signal 6 in this case specifies a divider ratioof 1:N₁, where N₁ is an integral number. As a result, the modulationsignal MS is injected with a (variable) frequency dividing ratio,determined by the modulation, via the DIV 15 into the feedback path. Afirst frequency division signal 7, which is present at the first inputof the PFD 11, is generated at the output of the DIV 15.

At a second input of the PFD 11 there is a reference signal with acorresponding reference frequency F_(REF). The reference frequencyF_(REF) may be generated for example by an oscillator crystal, which isnot represented. As a result, a signal which is characteristic of thedifference in frequency and/or phase between the reference signal andthe first frequency division signal 7 is generated at the output of thePFD 11. This output signal 9 of the PFD 11 is used for driving thecharge pump 12. A current which is dependent on the signal 9 with whichthe charge pump 12 is driven is generated in the charge pump 12. Withthe current generated in the charge pump 12, the loop filter 13 ischarged. The output signal of the loop filter 13 is a voltage signal andis present at the tuning input TE of the VCO 14.

An output signal AS, which is present at the first input of the DIV 15and is modulated by the first digital modulation signal 6, is generatedat the output of the VCO 14.

The compensating method is explained below on the basis of the PLLcircuit according to FIG. 1:

In a first step, the first digital modulation signal 6, with a firstconstant divider ratio of 1:N₁, is entered. The divider ratio 1:N₁ issuch that the PLL circuit 1 is tuned to a first frequency F₁, whichcorresponds to a channel center frequency f less a digital modulationamplitude Δf_(Dig).

Tuning the PLL circuit 1 to the frequency F₁=f−Δf_(Dig) produces at thetuning input TE of the VCO 14 a voltage value V₁ which corresponds tothis frequency F₁, for example in the case of a linear frequency voltagecharacteristic of the VCO 14 is proportional to this frequency F₁.

During this tuning of the PLL circuit 1 to the frequency F₁, thecompensating path 3 is deactivated, the second loop filter (LP2) 34being pre-charged to the fixed voltage value of zero. The switches 35and 36 are in the positions represented in FIG. 1, which in the case ofboth switches 35 and 36 are referred to as closed.

Once the tuning of the PLL circuit 1 to the frequency F₁ has beencompleted, the main path of the PLL circuit 1 is deactivated in a secondstep, in that the current from the charge pump 12 is set to the fixedvalue of zero and the control loop is consequently opened. In theprocess it is ensured by the integral action of the loop filter 13 thatthe voltage V₁ at the tuning input TE of the VCO 14 or at a summationpoint 141 remains virtually unchanged. This applies at least for theduration of the subsequent compensating operation. Furthermore, thecompensating path 3, that is to say the second charge pump 33 and thesecond loop filter 34, is then activated and, as a result, the controlloop is closed by means of the compensating path 3.

The switch position of the two switches 35 and 36 thereby remainsunchanged.

Subsequently, the programming unit 21 is reprogrammed, so that a seconddigital modulation signal 6′, which indicates a second constant dividerratio 1:N₂, is generated at the output of the programming unit 21.

The second divider ratio 1:N₂ is set in such a way that the outputsignal AS at the VCO 14 has a second frequency F₂=f+Δf_(Dig). The PLLcircuit is consequently tuned to the second frequency F₂. Since thevoltage value V₁ is still present at the tuning input TE, a voltagevalue V₂ that corresponds to twice the digital modulation amplitude2Δf_(Dig) is produced at the modulation input ME of the VCO 14.

This voltage value V₂ results from the fact that the output frequency atthe VCO 14 corresponds to the second frequency F₂, to which the PLLcircuit 1 is tuned. Therefore, at the frequency-generating unit 142there is a control signal SS, the voltage V₃ of which generates thisfrequency F₂. On account of the summation condition at the summationpoint 141 and the fixed voltage V₁ at the tuning input TE, a voltagevalue of V₂(2Δf_(Dig))=V₃(f+Δf_(Dig))−V₁(f−Δf_(Dig)) is thereforeobtained at the modulation input ME.

For comparing the differential signal 9′ at the output of the secondlow-pass filter 34 with an analog modulation signal, in a third step themodulation signal MS is converted by the DAC 22 into an analogmodulation signal 8 and is present at a second input of the analogmodulation unit 32. The analog modulation signal 8 brings about afrequency F₃=f+Δf_(Ana) at the output of the VCO. In the compensatedstate, the voltage value corresponding to this frequency F₃ at themodulation input ME must be half the voltage value V₂. For comparingwith the voltage value V₂, this voltage value is picked off at theoutput of the modulation unit 32 and, after doubling in the multiplier37, is applied as a comparison signal 8′ to a second input of thecomparison unit 31.

The voltage value V₂ of the differential signal 9′ is at the same timepresent at a first input of the comparison unit 31, which in theexemplary embodiment is configured as a comparator. The switch positionsremain unchanged, that is to say the comparison unit 31 and the analogmodulation unit 32 are decoupled from the modulation input ME of the VCO14 by the switch position of the first switch 35.

A deviation between the voltage value V₂ of the differential signal 9′and the corresponding voltage value of the comparison signal 8′ that isdetermined in the comparison unit 31 is eliminated, in that themodulation amplitude of the analog modulation signal provided at theoutput of the analog modulation unit 32 is changed.

Alternatively, the voltage V₂ at the input of the comparison unit 31,corresponding to the differential signal 9′, may be stored, for exampleby a capacitor, and subsequently compared with the voltage value of thecomparison signal 8′.

Once the compensating operation has been completed, the switch 35 isswitched over, the switch 36 is opened and the charge pump 33 and theloop filter 34 are deactivated. The main path of the PLL circuit 1 isactivated.

The PLL circuit 1 for the two-point modulation is then compensated andcan commence its operation. The digital modulation signal and the analogmodulation signal in this case superposed, and frequency-independenttransmission characteristics of the PLL circuit 1 are obtained as aresult of the compensating operation described.

The generating of the comparison signal 8′ may also be carried out inthe comparison unit 21 or in the analog modulation unit 32.

If an analog signal is used as the modulation signal MS, the modulationdevice 2 may also be configured for example in such a way that the DAC22 is not required, but instead a corresponding signal conversion iscarried out in the digital modulation path.

The compensating of the signals applied to the comparison unit 31 may beperformed for example in an iterative process. In this case, anapproximative compensation of the modulation amplitudes with alternateupdating of the comparison signal 8′ and assessment of the changedoutput signal then obtained from the comparison unit 31 takes place.When the difference in voltage has been eliminated at the comparisonunit 31, the compensation between the digital modulation amplitude andthe analog modulation amplitude is achieved.

It may also be provided that, during the compensation, the main path ofthe PLL circuit 1 is kept active, in that the first charge pump 12 isoperated with a small current. On account of the reduced current of thefirst charge pump 12, the main path of the PLL circuit 1 cannot followthe modulation and the voltage at the tuning input TE of the VCO 14remains constant. This allows the effect to be achieved that a voltageloss at the tuning input TE of the VCO 14 caused by leakage currentswhich may occur in the case of a deactivated main path are compensated.

In FIG. 2, a schematic flow diagram of the compensating method ispresented. In the first method step S1, the PLL circuit 1 (FIG. 1) 1 istuned to a frequency F₁=f−Δf_(Dig), in that the first digital modulationsignal 6 is injected into the main path of the PLL circuit 1. In thesubsequent second method step S2, the second digital modulation signal6′ is injected into the PLL circuit 1 and the PLL circuit is tuned tothe frequency F₂=f+Δf_(Dig). An output signal 9 is coupled out from thePLL circuit 1 and a differential signal 9′ is generated, saiddifferential signal being characteristic of the change in voltage of acontrol signal SS at the input of the frequency-generating unit 142 thatis brought about by the two digital modulation signals 6 and 6′. Thedifferential signal 9′ is compared with the comparison signal, which isproportional to the analog modulation signal 8, according to method stepS3. The deviation between the differential signal 9′ and the comparisonsignal 8′ that is determined in the comparison is eliminated, in thatthe analog modulation amplitude is changed in a way corresponding to themethod step S4.

1. A compensating method for a PLL circuit that functions according tothe principle of two-point modulation, comprising: (a) injecting a firstdigital modulation signal into the PLL circuit, the PLL circuit beingtuned to a first frequency, (b) injecting a second digital modulationsignal into the PLL circuit, the PLL circuit being tuned to a secondfrequency, which is different from the first frequency, (c) coupling outa differential signal, which is characteristic of a change of a controlsignal of a frequency-generating unit of the PLL circuit that is broughtabout by the two digital modulation signals, (d) comparing thedifferential signal with a comparison signal, which is characteristic ofa modulation amplitude of an analog modulation signal, and (e) changingthe modulation amplitude in such a way that a deviation between thedifferential signal and the comparison signal that is determined in thecomparison is eliminated.
 2. The method as claimed in claim 1, whereinthe injection of the first digital modulation signal causes the PLLcircuit to be tuned to the first frequency, which is formed bysubtracting a frequency of a variably selectable, digital modulationamplitude from a channel center frequency.
 3. The method as claimed inclaim 2, wherein the injection of the second digital modulation signalcauses the PLL circuit to be tuned to the second frequency, which isformed by adding the frequency of the variably selectable, digitalmodulation amplitude and the channel center frequency.
 4. The method asclaimed in claim 1, wherein a voltage value corresponding to the analogmodulation amplitude is multiplied by a factor of 2 for the comparisonwith the voltage value corresponding to the differential signal.
 5. Themethod as claimed in claim 1, wherein a compensating path contributingto the control signal generation is connected in parallel with a mainpath of the PLL circuit and further comprising: activating thecompensating path at least during the injection of the second digitalmodulation signal.
 6. The method as claimed in claim 5, furthercomprising: deactivating the main path of the PLL circuit after theinjection of the first digital modulation signal, wherein a currentgenerated by a first charge pump in the main path is set to the value ofzero.
 7. The method as claimed in claim 5, wherein the main path of thePLL circuit is kept active during the compensation and a current is setby a charge pump in the main path of the PLL circuit in such a way thatthe voltage at a tuning input of a VCO of the PLL circuit is keptsubstantially constant.
 8. The method as claimed in claim 1, wherein thefirst digital modulation signal and the second digital modulation signalare injected via a frequency divider DIV arranged in the feedback pathof the PLL circuit.
 9. A PLL circuit, which is designed for theinjection of an analog modulation signal and a digital modulation signalaccording to the principle of two-point modulation, the PLL circuithaving a compensation path connected in parallel with a main paththereof, the compensating path of the PLL circuit comprising: acoupling-out means for generating a differential signal, which ischaracteristic of a change of a control signal of a frequency-generatingunit of the PLL circuit when different digital modulation signals areinjected into the PLL circuit, a comparison unit for comparing thedifferential signal with a comparison signal, which is characteristic ofa modulation amplitude of an analog modulation signal, and a modulationunit, which changes the modulation amplitude of the analog modulationsignal in dependence on an output signal of the comparison unit.
 10. ThePLL circuit as claimed in claim 9, wherein the coupling-out meanscomprises a charge pump and a loop filter connected downstream of thecharge pump.
 11. The PLL circuit as claimed in claim 9, furthercomprising a first switch, by means of which the differential signal isapplied to a modulation input of a VCO of the PLL circuit.
 12. The PLLcircuit as claimed in claim 9, further comprising a second switch, inthe closed position of which the comparison signal is present at aninput of the comparison unit.
 13. A two-point modulator, comprising: aPLL circuit; a modulation circuit in a feedback path of the PLL circuit;and a compensation circuit in a compensation path of the PLL circuit,wherein the compensation circuit is configured to compare a differentialsignal that reflects a change of a control signal associated with afrequency generating circuit within the PLL circuit with a comparisonsignal that reflects a modulation amplitude of an analog modulationsignal, alter the modulation amplitude of the analog modulation signalbased on the comparison, and provide the analog modulation signal to thePLL circuit.
 14. The two-point modulator of claim 13, wherein themodulation circuit comprises a programmable modulation circuitconfigured to generate two different digital modulation control signalsbased on a digital modulation signal, and provide such signals to thePLL circuit for generation of a first frequency signal and a secondfrequency signal, respectively, by the frequency generating circuit. 15.The two-point modulator of claim 14, wherein the compensation circuit isconfigured to generate the differential signal based on the twodifferent digital modulation control signals.
 16. The two-pointmodulator of claim 14, further comprising a digital-to-analog converter,operable to convert a digital modulation signal to an analog modulationsignal for comparison within the comparison circuit.
 17. The two-pointmodulator of claim 13, wherein the compensation circuit is configured toalter the modulation amplitude of the analog modulation signal tosubstantially eliminate a deviation between the differential signal andthe comparison signal.